Product Descriptions
The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
Specifications
| Attribute | Attribute value |
| ANSM-Part# | ANSM-SN54LS112AJ |
| Category | Integrated Circuits (ICs) |
| Logic | |
| Flip Flops | |
| Mfr | onsemi |
| Series | 54LS |
| Package | Bulk |
| Product Status | Active |
| Function | Set(Preset) and Reset |
| Type | JK Type |
| Output Type | Complementary |
| Number of Elements | 2 |
| Number of Bits per Element | 1 |
| Clock Frequency | 45 MHz |
| Max Propagation Delay @ V, Max CL | 20ns @ 5V, 15pF |
| Trigger Type | Negative Edge |
| Current - Output High, Low | 400μA, 4mA |
| Voltage - Supply | 4.5V ~ 5.5V |
| Current - Quiescent (Iq) | 6 mA |
| Operating Temperature | ‘’-55°C ~ 125°C (TA) |
| Mounting Type | Through Hole |
| Supplier Device Package | 16-CDIP |
| Package / Case | 16-CDIP (0.300", 7.62mm) |
| Base Product Number | 54LS112 |
Actual product photos
Product Data Book：
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