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Product Features

Functional Description

? 3-to-8 Line Decoder

Features

(1) High speed: tpd = 14 ns (typ.) at VCC = 5 V

(2) Low power dissipation: ICC = 4.0 μA (max) at Ta = 25 

(3) Balanced propagation delays: tPLH ≈ tPHL

(4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V

Product General

 The 74HC238D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology.

 It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

 When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7) will go high.

 When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all the outputs go low. G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems.

 All inputs are equipped with protection circuits against static discharge or transient excess voltage.

Specifications

Actual product photos

Product Data Book：

For more product information, please download the PDF

Payment&Transportation

Official Certificate&Certificate

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