国模无码人体一区二区_自慰系列无码专区_国产成人AV综合色_精品一区二区无码免费

Product Descriptions

The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

Product Features

? 7.5 ns pin-to-pin logic delays on all pins

? fCNT to 125 MHz

? 108 macrocells with 2,400 usable gates

? Up to 108 user I/O pins

? 5V in-system programmable

- Endurance of 10,000 program/erase cycles

- Program/erase over full commercial voltage and temperature range

? Enhanced pin-locking architecture

? Flexible 36V18 Function Block

- 90 product terms drive any or all of 18 macrocells within Function Block

- Global and product term clocks, output enables, set and reset signals

? Extensive IEEE Std 1149.1 boundary-scan (JTAG) support

? Programmable power reduction mode in each macrocell

? Slew rate control on individual outputs

? User programmable ground pin capability

? Extended pattern security features for design protection

? High-drive 24 mA outputs

? 3.3V or 5V I/O capability

? Advanced CMOS 5V FastFLASH? technology

? Supports parallel programming of more than one XC9500 concurrently

? Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages

Specifications

Actual product photos

Product Data Book：

For more product information, please download the PDF

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

We also provide ：